3959
DMOS FULL-BRIDGE
PWM MOTOR DRIVER
FUNCTIONAL BLOCK DIAGRAM
V
DD
LOGIC
SUPPLY
CHARGE PUMP
BANDGAP
V
DD
C
REG
TSD
V
BB
+
CP1
CP2
LOAD
SUPPLY
BANDGAP
REGULATOR
V
REG
UNDER-
VOLTAGE &
FAULT DETECT
CHARGE
PUMP
SLEEP
EXT MODE
PHASE
ENABLE
CONTROL LOGIC
GATE DRIVE
CP
OUT
A
OUT
B
SENSE
ZERO
CURRENT
DETECT
TO V
DD
BLANK
PFD1
PFD2
ROSC
OSC
CURRENT
SENSE
C
S
R
S
PWM
TIMER
REFERENCE
BUFFER &
÷10
REF
V
REF
Dwg. FP-048-2A
CP
2
CP
1
PHASE
ROSC
GROUND
GROUND
GROUND
GROUND
LOGIC
SUPPLY
ENABLE
PFD
2
BLANK
1
2
3
4
5
θ
CHARGE PUMP
24
23
22
21
V
BB
20
19
18
17
CP
V
REG
SLEEP
OUT
B
LOAD
SUPPLY
GROUND
GROUND
SENSE
OUT
A
EXT MODE
REF
PFD
1
Dwg. PP-069-5A
A3959SB
(DIP)
Note that the A3959SLB (SOIC), A3959SB (DIP),
and A3959SLP (TSSOP) do not share a common
terminal assignment.
6
7
8
9
9
10
11
12
V
DD
LOGIC
16
15
÷
10
PWM TIMER
14
13
2
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 2001, 2003 Allegro MicroSystems, Inc.
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
