5841
AND
5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
FUNCTIONAL BLOCK DIAGRAM
(‘A’ Package Shown)
CLOCK
SERIAL
DATA IN
LOGIC
GROUND
2
V
DD
5
LOGIC
SUPPLY
SERIAL
DATA OUT
STROBE
OUTPUT ENABLE
(ACTIVE LOW)
3
SERIAL-PARALLEL SHIFT REGISTER
6
4
LATCHES
7
8
MOS
BIPOLAR
1
18
17
16
15
14
13
12
11
10
9
POWER
GROUND
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
K
SUB
Dwg. FP-013-2
ALLOWABLE PACKAGE POWER DISSIPATION IN WATTS
A5841SLW
& A5842SLW
POWER
GROUND
CLOCK
SERIAL
DATA IN
GROUND
LOGIC SUPPLY
SERIAL
DATA OUT
STROBE
OUTPUT
ENABLE
POWER
GROUND
NO
CONNECT.
1
SUB
2
3
4
5
6
7
8
9
SUB
10
NC
NC
11
NO
CONNECT.
ST
OE
V
DD
CLK
19
18
LATCHES
2.5
2.0
18-PIN DIP, R
θJA
= 60°C/W
20-LEAD SOIC, R
θJA
= 70°C/W
18-LEAD SOIC, R
θJA
= 80°C/W
20
OUT
1
OUT
2
OUT
3
OUT
4
OUT
5
OUT
6
OUT
7
OUT
8
K
1.5
SHIFT REGISTER
17
16
15
14
13
12
1.0
0.5
0
25
50
75
100
125
AMBIENT TEMPERATURE IN
°C
150
Dwg. PP-029-3
Dwg. GP-022-4
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright © 1985, 2000 Allegro MicroSystems, Inc.
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
