5841
AND
5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TRUTH TABLE
Serial
Shift Register Contents
Data Clock
Input Input I
1
I
2
I
3
.............. I
8
H
L
X
H
L
R
1
R
2
.............. R
7
R
1
R
2
.............. R
7
Serial
Data Strobe
Output Input
R
7
R
7
R
8
X
P
8
L
H
R
1
R
2
R
3
.............. R
8
P
1
P
2
P
3
.............. P
8
X
L = Low Logic Level
H = High Logic Level
X = Irrelevant
X
X
.............. X
L
H
P
1
P
2
P
3
..............
P
8
Latch Contents
I
1
I
2
I
3
.............. I
8
Output
Enable
Output Contents
I
1
I
2
I
3
..............
I
8
R
1
R
2
R
3
.............. R
8
X
X
X
.............. X
P
1
P
2
P
3
.............. P
8
H H H .............. H
P = Present State
R = Previous State
TYPICAL APPLICATION
RELAY/SOLENOID DRIVER
Using Split Supply
UCN5842A
The products described here are manufactured
under one or more U.S. patents or U.S. patents
pending.
Allegro MicroSystems, Inc. reserves the right to
make, from time to time, such departures from the detail
specifications as may be required to permit improve-
ments in the performance, reliability, or
manufacturability of its products. Before placing an
order, the user is cautioned to verify that the informa-
tion being relied upon is current.
Allegro products are not authorized for use as
critical components in life-support devices or systems
without express written approval.
The information included herein is believed to be
accurate and reliable. However, Allegro
MicroSystems, Inc. assumes no responsibility for its
use; nor for any infringement of patents or other rights
of third parties which may result from its use.
Dwg. No. A-12,547
www.allegromicro.com
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
