5841
AND
5842
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
TYPICAL INPUT CIRCUITS
V
DD
CLOCK
A
B
DATA IN
E
C
STROBE
F
D
STROBE
IN
OUTPUT
ENABLE
OUTPUT
ENABLE
OUT
N
G
Dwg. No. A-12,627
Dwg. EP-010-3
VDD
TIMING CONDITIONS
(T
A
= +25
°
C, V
DD
= 5.0 V, Logic Levels are V
DD
and Ground)
A.
Minimum Data Active Time Before Clock Pulse
(Data Set-Up Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75 ns
CLOCK
SERIAL
DATA IN
B.
Minimum Data Active Time After Clock Pulse
(Data Hold Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
75 ns
C.
Minimum Data Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 ns
D.
Minimum Clock Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
150 ns
E.
Minimum Time Between Clock Activation and Strobe . . . . . . . . . . . .
300 ns
F.
Minimum Strobe Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 ns
Dwg. EP-010-4A
G.
Typical Time Between Strobe Activation and
Output Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.0
µ
s
TYPICAL OUTPUT DRIVER
K
Serial Data present at the input is transferred to the shift register
on the logic “0” to logic “1” transition of the CLOCK input pulse. On
succeeding CLOCK pulses, the registers shift data information towards
the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the
input prior to the rising edge of the CLOCK input waveform.
Information present at any register is transferred to its respective
latch when the STROBE is high (serial-to-parallel conversion). The
latches will continue to accept new data as long as the STROBE is held
high. Applications where the latches are bypassed (STROBE tied high)
will require that the ENABLE input be high during serial data entry.
When the ENABLE input is high, all of the output buffers are
disabled (OFF) without affecting the information stored in the latches or
shift register. With the ENABLE input low, the outputs are controlled by
the state of the latches.
OUT
V
EE
SUB
Dwg. EP-021-8
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
ALLEGRO [ ALLEGRO MICROSYSTEMS ]
