AS7C1026
AS7C31026
®
Write cycle (over the operating range)
-10
Parameter
Write cycle time
Chip enable (CE) to write end
Address setup to write end
Address setup time
Write pulse width
Address hold from end of write
Data valid to write end
Data hold time
Write enable to output in high Z
Output active from write end
Byte select low to end of write
Shaded areas indicate preliminary information.
-12
–
–
–
–
–
–
–
–
6
–
–
12
8
9
0
8
0
6
0
–
1
8
–
–
–
–
–
–
–
–
6
–
–
-15
15
12
10
0
10
0
8
0
–
1
9
–
–
–
–
–
–
–
–
6
–
–
-20
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
4, 5
4, 5
Notes
20
13
12
0
12
0
10
0
–
2
12
–
–
–
–
–
–
–
–
8
–
–
Symbol Min Max Min Max Min Max Min Max
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
t
BW
10
8
8
0
8
0
5
0
–
1
8
SRAM
SRAM
Write waveform 1 (WE controlled)
t
WC
Address
t
CW
CE
t
BW
LB, UB
t
AS
WE
t
DW
Data
IN
t
WZ
Data
OUT
Data undefined
Data valid
t
OW
high Z
t
WC
Address
t
AS
CE
t
CW
t
AW
t
BW
LB, UB
t
WP
WE
t
DW
Data
IN
t
CLZ
Data
OUT
high Z
t
WZ
Data undefined
high Z
Data valid
t
OW
t
DH
t
WR
t
DH
t
AW
t
WP
t
WR
Write waveform 2 (CE controlled)
DID 11-20011-A. 5/22/00
ALLIANCE SEMICONDUCTOR
5
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
