AS7C1026
AS7C31026
®
Data retention characteristics (over the operating range)
Parameter
V
CC
for data retention
Data retention current
Chip deselect to data retention time
Operation recovery time
Input leakage current
Symbol
V
DR
I
CCDR
t
CDR
t
R
|I
LI
|
V
CC
= 2.0V
CE
≥
V
CC
–0.2V
V
IN
≥
V
CC
–0.2V or
V
IN
≤
0.2V
Test conditions
Min
2.0
–
0
t
RC
–
Max
–
500
–
–
1
Unit
V
µ
A
SRAM
ns
ns
µ
A
Data retention waveform
Data retention mode
V
CC
V
CC
t
CDR
CE
V
IH
V
DR
V
IH
V
DR
≥
2.0V
V
CC
t
R
AC test conditions
-
-
-
-
Output load: see Figure B or Figure C, except as noted.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
D
OUT
90%
10%
2 ns
90%
10%
255W
C(14)
GND
Figure B: 5V Output load
Thevenin Equivalent:
168W
+1.728V (5V and 3.3V)
D
OUT
+5V
480W
+3.0V
GND
D
OUT
255W
C(14)
+3.3V
320W
Figure A: Input pulse
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions,
Figures A, B, and C.
These parameters are specified with C
L
= 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
2V data retention applies to commercial temperature range operation only.
C=30pF, except all high Z and low Z parameters where C=5pF.
6
ALLIANCE SEMICONDUCTOR
DID 11-20011-A. 5/22/00
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
