Stratix Architecture
Figure 2–50 shows the global and regional clocking from the PLL outputs
and the CLK pins.
Figure 2–50. Global & Regional Clock Connections from Side Pins & Fast PLL Outputs Note (1), (2)
RCLK1
RCLK0
G1
G3
G8
G10
G11
RCLK9
RCLK8
G0
G2
G9
FPLL7CLK
FPLL10CLK
l0
PLL 7 l1
g0
l0
l1 PLL 10
g0
CLK10
CLK11
CLK0
CLK1
l0
PLL 1 l1
g0
l0
l1 PLL 4
g0
CLK8
CLK9
CLK2
CLK3
l0
l0
2
2
l1
l1
PLL 2
PLL 8
PLL 3
PLL 9
g0
g0
l0
l1
l0
l1
g0
g0
FPLL8CLK
FPLL9CLK
RCLK4
RCLK5
RCLK14
RCLK15
Global
Clocks
Regional
Clocks
Regional
Clocks
Notes to Figure 2–50:
(1) PLLs 1 to 4 and 7 to 10 are fast PLLs. PLLs 5, 6, 11, and 12 are enhanced PLLs.
(2) The global or regional clocks in a fast PLL’s quadrant can drive the fast PLL input. A pin or other PLL must drive
the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Figure 2–51 shows the global and regional clocking from enhanced PLL
outputs and top CLKpins.
Altera Corporation
July 2005
2–85
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
