Stratix Architecture
Enhanced PLLs
Stratix devices contain up to four enhanced PLLs with advanced clock
management features.
shows a diagram of the enhanced PLL.
Figure 2–52. Stratix Enhanced PLL
Post-Scale
Counters
VCO
Phase Selection
Selectable at
Each
PLL Output Port
From Adjacent PLL
Δt
Regional
Clocks
Clock
Switch-Over
Circuitry
INCLK0
/n
Δt
PFD
Charge
Pump
Loop
Filter
8
VCO
/g0
/l1
Phase
Frequency
Detector
Spread
Spectrum
4
Δt
Programmable
Time
Delay
on
Each
PLL Port
/l0
Δt
Global
Clocks
INCLK1
/g1
Δt
Δt
Δt
I/O buffers
(2)
To I/O buffers or
general
routing
(1)
Δt
/m
/g2
/g3
FBIN
Lock Detect
& Filter
VCO
Phase Selection
Affecting All
Outputs
/e0
Δt
Δt
Δt
Δt
I/O
Buffers
(3)
/e1
4
/e2
/e3
Notes to
(1)
(2)
(3)
(4)
External feedback is available in PLLs 5 and 6.
This single-ended external output is available from the
g0
counter for PLLs 11 and 12.
These four counters and external outputs are available in PLLs 5 and 6.
This connection is only available on EP1S40 and larger Stratix devices. For example, PLLs 5 and 11 are adjacent and
PLLs 6 and 12 are adjacent. The EP1S40 device in the 780-pin FineLine BGA package does not support PLLs 11
and 12.
Altera Corporation
July 2005
2–87
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
