I/O Structure
Figure 2–64. Stratix IOE in Bidirectional I/O Configuration Note (1)
Column or Row
Interconnect
ioe_clk[7..0]
I/O Interconnect
[15..0]
OE
OE Register
Output
Delay
D
Q
t
ZX
clkout
ENA
CLRN/PRN
OE Register
t
Delay
Output
Enable Clock
Enable Delay
CO
ce_out
V
CCIO
Optional
PCI Clamp
Output Clock
Enable Delay
V
CCIO
Programmable
Pull-Up
Resistor
aclr/prn
Chip-Wide Reset
Output Register
Logic Array
to Output
Register Delay
Output
Pin Delay
D
Q
Drive Strength Control
Open-Drain Output
Slew Control
sclr/preset
ENA
CLRN/PRN
Input Pin to
Logic Array Delay
Bus-Hold
Circuit
Input Pin to
Input Register Delay
Input Register
D
Q
clkin
ce_in
Input Clock
Enable Delay
ENA
CLRN/PRN
Note to Figure 2–64:
(1) All input signals to the IOE can be inverted at the IOE.
The Stratix device IOE includes programmable delays that can be
activated to ensure zero hold times, input IOE register-to-logic array
register transfers, or logic array-to-output IOE register transfers.
A path in which a pin directly drives a register may require the delay to
ensure zero hold time, whereas a path in which a pin drives a register
through combinatorial logic may not require the delay. Programmable
delays exist for decreasing input-pin-to-logic-array and IOE input
register delays. The Quartus II Compiler can program these delays to
automatically minimize setup time while providing a zero hold time.
Programmable delays can increase the register-to-pin delays for output
2–110
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
