I/O Structure
Figure 2–65. Stratix IOE in DDR Input I/O Configuration Note (1)
VCCIO
Column or Row
Interconnect
ioe_clk[7..0]
(1)
Optional
To DQS Local
Bus (3)
PCI Clamp
I/O Interconnect DQS Local
[15..0] Bus (1), (2)
(1)
VCCIO
Programmable
Pull-Up
Resistor
Input Pin to
Input Register Delay
sclr
Input Register
D
Q
clkin
ENA
CLRN/PRN
Output Clock
Enable Delay
Bus-Hold
Circuit
aclr/prn
Chip-Wide Reset
Latch
D Q
Input Register
D
Q
ENA
ENA
CLRN/PRN
CLRN/PRN
Notes to Figure 2–65:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
2–112
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
