I/O Structure
Figure 2–67. Stratix IOE in DDR Output I/O Configuration Notes (1), (2)
Column or Row
Interconnect
IOE_CLK[7..0]
I/O Interconnect
[15..0]
OE Register
D
Q
Output
Delay
t
ZX
clkout
ENA
CLRN/PRN
OE Register
Delay
Output
Enable Clock
Enable Delay
t
CO
Output Clock
Enable Delay
aclr/prn
V
CCIO
Optional
PCI Clamp
Chip-Wide Reset
OE Register
V
CCIO
D
Q
Programmable
Pull-Up
Resistor
sclr
Used for
DDR SDRAM
ENA
CLRN/PRN
Output Register
Logic Array
to Output
D
Q
Register Delay
Output
Pin Delay
clk
ENA
CLRN/PRN
Drive Strength Control
Open-Drain Output
Slew Control
Output Register
Logic Array
to Output
Register Delay
D
Q
Bus-Hold
Circuit
ENA
CLRN/PRN
Notes to Figure 2–67:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tristate is by default active high. It can, however, be designed to be active low.
2–114
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
