DC & Switching Characteristics
Table 4–130. Enhanced PLL Specifications for -8 Speed Grade (Part 3 of 3)
Symbol
Parameter
Min Typ
Max
Unit
tLSKEW
Clock skew between two external
clock outputs driven by the same
counter
50
ps
tSKEW
Clock skew between two external
clock outputs driven by the different
counters with the same settings
75
ps
fSS
Spread spectrum modulation
frequency
30
0.5
10
150
0.6
kHz
%
% spread
tARESET
Percentage spread for spread
spectrum frequency (10)
ns
Minimum pulse width on areset
signal
Notes to Tables 4–127 through 4–130:
(1) The minimum input clock frequency to the PFD (fIN/N) must be at least 3 MHz for Stratix device enhanced PLLs.
(2) Use this equation (fOUT = fIN * ml(n × post-scale counter)) in conjunction with the specified fINPFD and fV CO ranges
to determine the allowed PLL settings.
(3) See “Maximum Input & Output Clock Rates” on page 4–76.
(4) tFCOMP can also equal 50% of the input clock period multiplied by the pre-scale divider n (whichever is less).
(5) This parameter is timing analyzed by the Quartus II software because the scanclkand scandataports can be
driven by the logic array.
(6) Actual jitter performance may vary based on the system configuration.
(7) Total required time to reconfigure and lock is equal to tDLOCK + tCONFIG. If only post-scale counters and delays are
changed, then tDLOCK is equal to 0.
(8) When using the spread-spectrum feature, the minimum VCO frequency is 500 MHz. The maximum VCO
frequency is determined by the speed grade selected.
(9) Lock time is a function of PLL configuration and may be significantly faster depending on bandwidth settings or
feedback counter change increment.
(10) Exact, user-controllable value depends on the PLL settings.
(11) The LOCK circuit on Stratix PLLs does not work for industrial devices below -20C unless the PFD frequency > 200
MHz. See the Stratix FPGA Errata Sheet for more information on the PLL.
Altera Corporation
July 2005
4–99
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
