PLL Specifications
Tables 4–131 through 4–133 describe the Stratix device fast PLL
specifications.
Table 4–131. Fast PLL Specifications for -5 & -6 Speed Grade Devices
Symbol
Parameter
CLKIN frequency (1), (2), (3)
Input frequency to PFD
Min
10
Max
717
500
420
Unit
MHz
MHz
MHz
fIN
fINPFD
fOUT
10
Output frequency for internal global or 9.375
regional clock (3)
fOUT_DIFFIO
Output frequency for external clock
driven out on a differential I/O data
channel (2)
(5)
(5)
fVCO
VCO operating frequency
300
40
1,000
60
MHz
%
tINDUTY
tINJITTER
tDUTY
CLKIN duty cycle
Period jitter for CLKIN pin
200
55
ps
Duty cycle for DFFIO 1× CLKOUT pin (6)
Period jitter for DIFFIO clock out (6)
Time required for PLL to acquire lock
Multiplication factors for m counter (6)
45
%
tJITTER
tLOCK
(5)
ps
10
1
100
32
µs
m
Integer
Integer
l0, l1, g0
Multiplication factors for l0, l1, and g0
counter (7), (8)
1
32
tARESET
10
ns
Minimum pulse width on areset
signal
Table 4–132. Fast PLL Specifications for -7 Speed Grades (Part 1 of 2)
Symbol
Parameter
CLKIN frequency (1), (3)
Input frequency to PFD
Min
10
Max
640
500
420
Unit
MHz
MHz
MHz
fIN
fINPFD
fOUT
10
Output frequency for internal global or 9.375
regional clock (4)
fOUT_DIFFIO
Output frequency for external clock
driven out on a differential I/O data
channel
(5)
(5)
MHz
fVCO
VCO operating frequency
CLKIN duty cycle
300
40
700
60
MHz
%
tINDUTY
tINJITTER
tDUTY
Period jitter for CLKIN pin
200
55
ps
Duty cycle for DFFIO 1× CLKOUT pin (6) 45
%
4–100
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
