440GP – Power PC 440GP Embedded Processor
Revision 1.07 – October 4, 2007
Data Sheet
Recommended DC Operating Conditions
Device operation beyond the conditions specified is not recommended. Extended operation beyond the recommended
conditions can affect device reliability.
Parameter
Logic Supply Voltage
I/O Supply Voltage
DDR SDRAM Supply Voltage (DDR clock up to 166MHz)
PLL Supply Voltages
DDR SDRAM Reference Voltage
Input Logic High (2.5V SSTL)
Input Logic High (3.3V PCI-X)
Symbol
V
DD
OV
DD
SV
DD
AxV
DD
SV
REF
Minimum
+1.7
+3.0
+2.3
+1.65
+1.15
SV
REF
+0.18
Typical
+1.8
+3.3
+2.5
+1.8
+1.25
Maximum
+1.9
+3.6
+2.7
+1.95
+1.35
SV
DD
+0.3
OV
DD
+0.5
+5.5
SV
REF
-0.18
0.35OV
DD
+0.8
SV
DD
OV
DD
OV
DD
0.55
0.1OV
DD
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Notes
4
4
4
3
3
2
1
V
IH
Input Logic High (3.3V LVTTL, 5V tolerant receiver)
Input Logic Low (2.5V SSTL)
Input Logic Low (3.3V PCI-X)
V
IL
Input Logic Low (3.3V LVTTL, 5V tolerant receiver)
Output Logic High (2.5V SSTL)
Output Logic High (3.3V PCI-X)
V
OH
Output Logic High (3.3V LVTTL, 5V tolerant receiver)
Output Logic Low (2.5V SSTL)
Output Logic Low (3.3V PCI-X)
V
OL
Output Logic Low (3.3V LVTTL, 5V tolerant receiver)
Input Leakage Current (No pull-up or pull-down)
Input Leakage Current for Pull-Down
Input Leakage Current for Pull-Up
Input Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
Input Max Allowable Undershoot (3.3V LVTTL, 5V tolerant
receiver)
Output Max Allowable Overshoot (3.3V LVTTL, 5V tolerant
receiver)
Output Max Allowable Undershoot (3.3V LVTTL,
5V tolerant receiver)
I
IL1
I
IL2
I
IL3
V
IMAO
V
IMAU
V
OMAO
V
OMAU3
0.5OV
DD
+2.0
-0.3
-0.5
0
+1.95
0.9OV
DD
+2.4
0
1
1
1
0
0
0 (LPDL)
-150 (LPDL)
+0.4
0
200 (MPUL)
0 (MPUL)
+5.5
μ
A
μ
A
μ
A
V
V
5
5
-0.6
+5.5
-0.6
V
V
58
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
