Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Notes:
1. All of the DQS signals are referenced to MemClkOut0(0).
2. The T
DS
values in the table include 3/4 of a cycle at the indicated clock speed.
3. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle
time for the lower clock frequency (T
DS
- 5.625 + 0.75T
CYC
).
T
DS
(ns)
Clock Speed (MHz)
Signal Name
Minimum
133
133
133
133
133
133
133
133
133
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
na
na
na
na
na
na
na
na
na
Maximum
6.25
6.25
6.25
6.25
6.25
6.25
6.25
6.25
6.25
I/O Timing—DDR SDRAM T
DS
Notes:
1. T
SK
is referenced to MemClkOut0(0). T
SA
and T
HA
are referenced to MemClkOut0(90).
2. To obtain adjusted T
SA
values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and
subtract T
SK
maximum (0.75T
CYC
- T
SK
max).
3. To obtain adjusted T
HA
values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add
T
SK
minimum (0.25T
CYC
+ T
SK
min).
T
SK
(ns)
Clock Speed (MHz)
Signal Name
Minimum
133
133
133
133
133
133
133
MemAddr00:12
BA0:1
BankSel0:3
ClkEn0:3
CAS
RAS
WE
0.4
0.4
0.4
0.4
0.4
0.4
0.4
Maximum
1.2
1.2
1.2
1.2
1.2
1.2
1.2
Minimum
4.425
4.425
4.425
4.425
4.425
4.425
4.425
Minimum
2.275
2.275
2.275
2.275
2.275
2.275
2.275
T
SA
(ns)
T
HA
(ns)
I/O Timing—DDR SDRAM T
SK
, T
SA
, and T
HA
AMCC
73
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
