Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 1:
If the data-to-PLB clock timing is as shown in the example below, then the read clock is not delayed and the Stage
1 data is sampled at
(1).
Except for small, low frequency memory systems with the memory located physically
close to the PPC440GP, it is unlikely that Stage 1 data can be sampled. When the data comes later, it is necessary
to sample Stage 2 or Stage 3 data. (see Examples 2 and 3). Another way to get the desired data-to-PLB timing to
allow Stage 1 sampling is to buffer MemClkOut0 and skew it enough to guarantee the timing. In this example
T
T
= 1.5ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 1
DQS at pin
Data at pin
D0
T
SIN
DQS Stage 1 C
D1
D2
D3
Data in Stage 1 D
T
DIN
D0
T
P
T
P
High
D1
D2
D3
D0
D0
D1
D0
D0
D1
D2
D2
D2
D3
D2
D3
Data out Stage 1
Low
Data in at RDSP
with no ECC
High
Low
T
T
PLB Clock
High
Data out RDSP
Low
D0
D1
D2
D3
(1)
T
SIN
= Delay from DQS at package pin to C on Stage 1 FF.
T
P
= Propagation delay through FFs
T
DIN
= Delay from data at package pin to D on Stage 1 FF.
T
T
= Propagation delay, Stage 1 input to RDSP input w/o ECC
AMCC
77
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
