Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
DDR SDRAM MemClkOut0 and Read Clock Delay
PLB Clk
MemClkOut0(0)
T
MD
T
MD
min =
850ps
T
MD
max =
2600ps
Read Clock
T
RD
T
RD
min =
0ps
T
RD
max =
300ps
In operation, following the receipt of an address and read command from the PPC440GP, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440GP using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
DDR SDRAM Read Data Path
Package pins
Mux
D
RDSP
Q
Stage 1
D
Stage 2
Q
D
Q
D
Stage 3
Q
ECC
FF
PLB bus
Data
FF,
XL
C
FF
FF
C
C
C
DQS
1/4
Cycle
Delay
PLB Clock
Programmed
Read Clock
Delay
Read Select
(SDRAM0_TR1)
FF Timing:
T
IS
= Input setup time = 0.2ns
T
IH
= Input hold time = 0.1ns
T
P
= Propagation delay (D to Q or C to Q) =
0.6ns maximum
FF: Flip-Flop
XL: Transparent Latch
AMCC
75
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
