Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Example 3:
In this example, ECC is enabled. This requires that Stage 3 data be sampled at
(3).
If ECC is disabled, the system
will still work, but there will be more latency before the data is sampled into RDSP. Again, T
T
= 1.5ns and T
TE
=
4.3ns at worst case conditions.
DDR SDRAM Read Cycle Timing—Example 3
DQS at pin
Data at pin
D0
T
SIN
D1
D2
D3
DQS Stage 1 C
Data in Stage 1 D
T
DIN
D0
D1
D2
D3
T
P
High
Data out Stage 1
Low
D0
D1
D2
D3
D0
D2
PLB Clock
Read Clock Delayed
T
P
High
Data out Stage 2
Low
High
Low
T
TE
Data in at RDSP
with ECC
High
Low
D0
D1
D0
D1
D2
D3
D2
D3
D0
D1
D0
D1
D2
D3
D2
D3
Data out Stage 3
with ECC
Data out RDSP
with ECC
High
Low
(3)
T
T
= Propagation delay from Stage 2 input to RDSP input w/o ECC
T
TE
= Propagation delay from Stage 2 input to RDSP input with ECC
AMCC
79
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
