Revision 1.16 – July 19, 2006
440GR – PPC440GR Embedded Processor
Preliminary Data Sheet
Signal Descriptions
The PPC440GR embedded controller is packaged in a 456-ball enhanced plastic ball grid array (E-PBGA). The
following tables describe the package level pinout.
Table 5. Pin Summary
Group
Signal pins, non-multiplexed
Signal pins, multiplexed
Total Signal Pins
AV
DD
SAV
DD
SAGnd
AGnd
OV
DD
SV
DD
V
DD
Gnd
Total Power Pins
Reserved
Total Pins
No. of Pins
221
62
283
1
1
1
1
18
18
32
80
152
21
456
In the table “Signal Functional Description” on page 50, each I/O signal is listed along with a short description of its
function. Active-low signals (for example, RAS) are marked with an overline. Please see “Signals Listed
Multiplexed Signals
Some signals are multiplexed on the same pin so that the pin can be used for different functions. In most cases,
the signal names shown in this table are not accompanied by signal names that may be multiplexed on the same
pin. If you need to know what, if any, signals are multiplexed with a particular signal, look up the name in “Signals
programmed to serve the same function. The flexibility of multiplexing allows a single chip to offer a richer pin
selection than would otherwise be possible. The circuit type for multiplexed signals is shown as “Multiplex.” The
actual circuit type is the same as the primary signal.
Multipurpose Signals
In addition to multiplexing, some pins are also multi-purpose. For example, the EBC peripheral controller address
pins (PerAddr) are used as outputs by the PPC440GR to broadcast an address to external slave devices when the
PPC440GR has control of the external bus. When during the course of normal chip operation an external master
gains ownership of the external bus, these same pins are used as inputs which are driven by the external master
and received by the EBC in the PPC440GR. In this example, the pins are also bidirectional, serving both as inputs
and outputs.
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