440GR – PPC440GR Embedded Processor
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
Table 7. Signal Functional Description (Sheet 2 of 8)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
DDR SDRAM Interface
BA0:1
BankSel0:3
CAS
ClkEn
DM0:3
DM8
DQS0:3
DQS8
ECC0:7
MemAddr00:12
MemClkOut0
MemClkOut0
MemData00:31
MemSelfRef
RAS
WE
S
VREF1
S
VREF2A:B
Bank Address supporting up to four internal banks.
Selects up to four external DDR SDRAM banks.
Column Address Strobe.
Clock Enable.
Memory write data byte lane masks. DM8 is the byte lane
mask for the ECC byte lane.
Byte lane data strobe. DQS8 is the data strobe for the ECC
byte lane.
ECC check bits 0:7.
Memory address bus.
Subsystem clock.
Memory data bus.
Self refresh.
Row Address Strobe.
Write Enable.
SSTL reference voltage.
Supplemental SSTL reference voltage.
O
O
O
O
O
I/O
I/O
O
O
I/O
I
O
O
I
I
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
2.5V SSTL_2
Diff driver
2.5V SSTL_2
3.3V tolerant
2.5V CMOS
2.5V SSTL_2
2.5V SSTL_2
Volt ref receiver
Volt ref pin
(supplemental)
5
Description
I/O
Type
Notes
AMCC Proprietary
51
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
