S2042/S2043
S2043 Pin Assignment and Descriptions
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Pin Name
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
LOCKDETN
Level
TTL
I/O
O
Pin #
45
43
42
40
38
37
35
34
32
31
29
28
25
24
22
21
18
17
15
14
52
Description
Parallel data outputs. The width of the parallel data bus is
selected by the state of the DWS pin. Parallel data on this bus is
clocked out on the falling edge of RCLK in 20-bit mode and on
both the falling edges of RCLK and RCLKN in 1062.5 Mbit/sec,
10-bit mode. In 20-bit mode, D0 is the first bit received. In 10-bit
mode, D10-D19 are used and D0-D9 are driven to the high
state. In 10-bit mode, D10 is the first bit received.
TTL
O
When LOW, LOCKDETN indicates that the PLL is locked to the
incoming data stream. When HIGH, it provides a system flag
indicating that the PLL is locked to the local reference clock.
When HIGH, LPEN selects the loopback differential serial input
pins. When LOW, LPEN selects RX and RY (normal operation).
The level on this pin selects the parallel data bus width. When
LOW, a 20-bit parallel bus width is selected, and D(0-19) are
active. When HIGH, a 10-bit parallel data bus is selected, D(10-
19) are active and D(0-9) will go HIGH. (See Table 4.) A rising
edge will reset the internal counters (used for test).
Parallel data is clocked out on the falling edge of RCLK/RCLKN
(see Timing Diagrams in Figures 15-18). After a sync word is
detected, the period of the current RCLK and RCLKN is
stretched to align with the word boundary. (See Table 4 for
frequency.)
(Externally capacitively coupled.) A free-running crystal-
controlled reference clock for the PLL clock multiplier. The
frequency of REFCLK is set by the REFSEL pin. (See Table 4.)
Upon detection of a valid sync symbol, this output goes high for
one RCLK period. When sync is active, the sync symbol shall be
present on the parallel data bus bits D0-D9 in 20-bit mode and
D10-D19 in 10-bit mode.
(Externally capacitively coupled.) The serial loopback data
inputs. RLX is the positive input, and RLY is the negative input.
(Externally capacitively coupled.) The received serial data
inputs. RX is the positive input, and RY is the negative input.
LPEN
DWS
TTL
Static
TTL
I
I
8
4
RCLK
RCLKN
Diff.
TTL
O
49
48
REFCLK
Analog
I
2
SYNC
TTL
O
51
RLX
RLY
RX
RY
Diff.
PECL
Diff.
PECL
I
11
12
9
10
I
8
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
