S2042/S2043
S2042 Pin Assignment and Descriptions
HIGH PERFORMANCE SERIAL INTERFACE CIRCUITS
Pin Name
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TEST
Level
TTL
I/O
I
Pin #
50
49
48
47
44
43
42
41
38
37
36
35
31
30
29
28
25
24
23
22
20
Description
Accepts parallel input data. Data is clocked in on the rising edge
of REFCLK. In 20-bit mode, D0 is transmitted first. In 10-bit
mode, D10-19 are used, D0-D9 are ignored, and D10 is
transmitted first.
Static
Multi-
Level
TTL
TTL
I
Multilevel input used for factory testing. When not connected,
REFCLK replaces the internal bit clock to facilitate factory
testing. In normal use, this input is wired to ground.
The level on this pin selects the parallel data bus width. When
LOW, a 20-bit parallel bus width is selected, and D(0-19) are
active. When HIGH, a 10-bit parallel data bus is selected, D(10-
19) are active and D(0-9) are not used. (See Table 1.) A rising
edge will reset the part (used for test).
(Externally capacitively coupled.) A crystal-controlled reference
clock for the PLL clock multiplier. The frequency of REFCLK is
set by the REFSEL pin. (See Table 1.)
Differential TTL word rate clock true and complement. See
Table 1 for frequency.
Differential PECL outputs that transmit the serial data and drive
75W or 50W termination to Vcc-2V. Enabled by OE0. TX is the
positive output, and TY is the negative output.
Differential PECL outputs that are functionally equivalent to TX
and TY. They are intended to be used for loopback testing.
Enabled by OE1.
DWS
I
19
REFCLK
PECL
I
16
TCLK
TCLKN
TY
TX
TLX
TLY
Diff.
TTL
Diff.
PECL
Diff.
PECL
O
12
11
9
8
5
4
O
O
6
Applied Micro Circuits Corporation
6195 Lusk Blvd., San Diego, CA 92121 • (619) 450-9333
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
