D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
Table 1.
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device.
lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Device Bus Operations
DQ8–DQ15
Operation
Read
Write (Program/Erase)
Accelerated Program
Standby
Output Disable
Reset
Sector Group Protect
Sector Group Unprotect
Temporary Sector Group
Unprotect
CE#
L
L
L
V
CC
±
0.3 V
L
X
L
OE#
L
H
H
X
H
X
H
WE# RESET#
H
L
L
X
H
X
L
H
H
H
V
CC
±
0.3 V
H
L
V
ID
WP#
ACC
Addresses
A
IN
A
IN
A
IN
X
X
X
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L
A
IN
DQ0–
DQ7
D
OUT
BYTE#
= V
IH
D
OUT
BYTE#
= V
IL
DQ8–DQ14
= High-Z,
DQ15 = A-1
High-Z
High-Z
High-Z
X
X
X
X
X
H
X
X
V
HH
H
X
X
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
L
H
L
V
ID
H
X
X
X
X
X
X
V
ID
H
X
High-Z
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5 V, V
HH
= 11.5–12.5V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A23:A0 in word mode; A23:A-1 in byte mode. Sector addresses are A23:A15 in both modes.
2. The sector group protect and sector unprotect functions may also be implemented via programming equipment. See the
section.
3. If WP# = V
IL
, the first or last sector group remains protected. If WP# = V
IH
, the first or last sector will be protected or unprotected as
determined by the method described in “Write Protect (WP#)”. All sectors are unprotected when shipped from the factory (The
SecSi Sector may be factory protected depending on version ordered.)
4. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word con-
figuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
VersatileIO
TM
(V
IO
) Control
The VersatileIO
TM
(V
IO
) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V
IO
. See
for V
IO
options on this device.
December 16, 2005
Am29LV256M
9
AMD [ ADVANCED MICRO DEVICES ]
