s
The ROM/Flash memory interface provides the flex-
ibility to optimize the performance of ROM cycles,
including the support of burst-mode ROMs. This is
ben efi ci al bec aus e p ro duc ts bas ed on th e
ÉlanSC400 and ÉlanSC410 microcontrollers may
be implemented such that the operating system or
application programs are executed from ROM.
s
Because the microcontrollers support a large num-
ber of external buses and interfaces, the address
and data buses are shared between the various in-
terfaces to reduce pin count on the chip.
These features result in a versatile architecture that
can use various combinations of data bus sizes to
achieve cost and performance goals. The architecture
provides maximum performance and flexibility for high-
end vertical applications, but contains functionality for
a wider horizontal market that may demand less
performance.
s
A typical lower performance/lower cost system
might implement 16-bit DRAM banks, an 8-bit ISA
bus, an 8/16-bit PC Card bus, and use the internal
graphic controller.
s
A higher performance, full-featured system might
include 32-bit DRAM, VL-bus to an external graph-
ics controller, and a 16-bit ISA/PC Card bus.
The following basic data bus configuration rules apply.
(A complete list of feature trade-offs to be considered
in system design can be found in “System Consider-
s
When the internal graphics controller on the
ÉlanSC400 microcontroller is enabled, DRAM is al-
ways 16 bits wide, and no 32-bit targets are sup-
ported. This is because the graphics controller
needs a guaranteed short latency for adequate
video performance. If either 32-bit DRAMs, 32-bit
ROMs, or the VL-bus is enabled, the internal graph-
ics controller is unavailable.
Note that, as a derivative of the original ÉlanSC400 mi-
crocontroller, the ÉlanSC410 microcontroller shares
the primary architectural characteristics of the
ÉlanSC400 microcontroller described above, minus
the graphics controller and PCMCIA interfaces.
The following sections provide an overview of the fea-
tures of the ÉlanSC400 and ÉlanSC410 microcontrollers,
including on-chip peripherals and system interfaces.
tem performance by significantly reducing traffic on
the DRAM bus.
s
System management mode (SMM) facilitates de-
signs requiring power management by providing a
mechanism to control power to unneeded peripher-
als transparently to application software.
To reduce power consumption, the floating-point unit
has been removed from the Am486 CPU core. Float-
ing-point instructions are not supported on the
ÉlanSC400 and ÉlanSC410 microcontrollers, although
normal software emulation can be easily implemented.
The ÉlanSC400 and ÉlanSC410 microcontrollers use
the industry-standard 486 instruction set. Software
written for the 486 microprocessor and previous mem-
bers of the x86 architecture family can run on the
ÉlanSC400 and ÉlanSC410 microcontrollers.
Power Management
Power management on the ÉlanSC400 and
ÉlanSC410 microcontrollers includes a dedicated
power management unit and additional power man-
agement features built into each integrated peripheral.
The ÉlanSC400 and ÉlanSC410 microcontrollers can
use the following techniques to conserve power:
s
Slow down clocks when the system is not in active use
s
Shut off clocks to parts of the chip that are idle
s
Switch off power to parts of the system that are idle
s
Automatically reduce power use when batteries are low
The power management unit (PMU) controls stopping
and changing clocks, SMI generation, timers, activities,
and battery-level monitoring. It provides:
s
Hyper-Speed, High-Speed, Low-Speed, Temporary
Low-Speed, Standby, Suspend, and Critical
Suspend modes
s
Dynamically adjusted clock speeds for power
reduction
s
Programmable activity and wake-up monitoring
s
General-purpose I/O signals to control external
devices and external power management
s
Battery low and AC power monitoring
s
SMI/NMI synchronization and generation
Clock Generation
The ÉlanSC400 and ÉlanSC410 microcontrollers re-
quire only one 32.768-kHz crystal to generate all the
other clock frequencies required by the system. The
output of the on-chip crystal oscillator circuit is used to
generate the various frequencies by utilizing four
Phase-Locked Loop (PLL) circuits (three for the
ÉlanSC410 microcontroller). An additional PLL in the
CPU is used for Hyper-Speed mode.
Low-Voltage Am486 CPU Core
The ÉlanSC400 and ÉlanSC410 microcontrollers are
based on the low-voltage Am486 CPU core. The core
includes the following features:
s
2.7–3.3-V operation reduces power consumption
s
Industry-standard 8-Kbyte unified code and data
write-back cache improves both CPU and total sys-
14
Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ ADVANCED MICRO DEVICES ]
