D A T A
S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
Table 1.
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the re-
sulting output. The following subsections describe
each of these operations in further detail.
Am29LV160D Device Bus Operations
DQ8–DQ15
Addresses
(Note 1)
IN
A
IN
X
X
X
Sector Address,
A6 = L, A1 = H,
A0 = L
Sector Address,
A6 = H, A1 = H,
A0 = L
A
IN
DQ0–
DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
D
IN
BYTE#
= V
IH
D
OUT
D
IN
High-Z
High-Z
High-Z
X
BYTE#
= V
IL
DQ8–DQ14 = High-Z,
DQ15 = A-1
High-Z
High-Z
High-Z
X
Operation
Read
Write
Standby
Output Disable
Reset
Sector Protect (Note 2)
CE#
L
L
V
CC
±
0.3 V
L
X
L
OE# WE# RESET#
L
H
X
H
X
H
H
L
X
H
X
L
H
H
V
CC
±
0.3 V
H
L
V
ID
Sector Unprotect (Note 2)
Temporary Sector
Unprotect
L
X
H
X
L
X
V
ID
V
ID
D
IN
D
IN
X
D
IN
X
High-Z
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = V
IH
), A19:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
The internal state machine is set for reading array
data upon device power-up, or after a hardware re-
set. This ensures that no spurious alteration of the
memory content occurs during the power transition.
No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that
assert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
IH
. The BYTE# pin determines whether the
device outputs array data in words or bytes.
22358B7 May 5, 2006
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
Am29LV160D
9
AMD [ ADVANCED MICRO DEVICES ]
