LP62S16512-T Series
Preliminary
Features
n
Operating voltage: 2.7V to 3.6V
n
Access times: 55/70 ns (max.)
n
Current:
Very low power version: Operating: 50mA (max.)
Standby:
20µA (max.)
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Full static operation, no clock or refreshing required
n
All inputs and outputs are directly TTL-compatible
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Common I/O using three-state output
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Data retention voltage: 2.0V (min.)
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Available in 48-ball CSP (8
×
10mm) packages
512K X 16 BIT LOW VOLTAGE CMOS SRAM
General Description
The LP62S16512-T is a low operating current 8,388,608-
bit static random access memory organized as 524,288
words by 16 bits and operates on low power voltage from
2.7V to 3.6V. It is built using AMIC's high performance
CMOS process.
Inputs and three-state outputs are TTL compatible and
allow for direct interfacing with common system bus
structures.
Two chip enable input is provided for POWER-DOWN,
device enable. Two byte enable inputs and an output
enable input are included for easy interfacing.
Data retention is guaranteed at a power supply voltage
as low as 2.0V.
Product Family
Product
Family
LP62S16512
Operating
Temperature
-40°C ~ +85°C
VCC
Range
2.7V~3.6V
Power Dissipation
Speed
55ns / 70ns
Data Retention
(I
CCDR
, Typ.)
0.3µA
Standby
(I
SB1
, Typ.)
0.5µA
Operating
(I
CC2
, Typ.)
4mA
Package
Type
48 CSP
1. Typical values are measured at VCC = 3.0V, T
A
= 25°C and not 100% tested.
2. Data retention current VCC = 2.0V.
Pin Configurations
n
CSP (Chip Size Package)
48-pin Top View
1
A
B
C
D
E
F
G
H
LB
I/O
9
I/O
10
GND
VCC
I/O
15
I/O
16
A18
2
OE
HB
I/O
11
I/O
12
I/O
13
I/O
14
NC
A8
3
A0
A3
A5
A17
NC
A14
A12
A9
4
A1
A4
A6
A7
A16
A15
A13
A10
5
A2
CS
1
I/O
2
I/O
4
I/O
5
I/O
6
WE
A11
6
CS
2
I/O
1
I/O
3
VCC
GND
I/O
7
I/O
8
NC
PRELIMINARY
(March, 2002, Version 0.2)
1
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
