AS1910 - AS1915
Data Sheet - D e t a i l e d D e s c r i p t i o n
8 Detailed Description
The AS1910 - AS1915 supervisory circuits were designed to generate a reset when one of the two monitored supply
voltages falls below its factory-trimmed trip threshold (see V
TH
on
and V
TH2
on
and to maintain the
reset for a minimum timeout period (see t
RP
on
after all supplies have stabilized.
The integrated watchdog timer
helps mitigate against bad programming code or
clock signals, and/or poor peripheral response. An active-low manual reset input
allows for an externally activated system reset.
RESET/RESETN
Whenever one of the monitored voltages falls below its reset threshold, the RESET output (AS1910, AS1912, AS1913,
AS1915) asserts low or the RESETN output (AS1911, AS1914) asserts high. Once all monitored voltages have stabi-
lized, an internal timer keeps the reset asserted for the reset timeout period (t
RP
). After the t
RP
period, the RESET or
RESETN output return to their original state
Figure 9. Functional Diagram of V
CC
Supervisory Application
6
V
CC
AS1913/AS1914/AS1915
Reset Timeout
Delay Generator
1
RESETN/
RESET
+
–
0.63V
1.26V
5
V
CC2
V
CC
3
MRN
4
WDI
Watchdog Transition
Detector
Watchdog
Timer
2
GND
Figure 10. Reset Timing Diagram
V
CC
1V
V
TH
V
TH
1V
RESETN
t
RP
t
RD
RESET
GND
t
RP
t
RD
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