switching long enough to trigger the next power-down.
(Note that the tPD is approximately 5 ns. slower on the first
transition from sleep mode.)
As a result of the "Zero-Power" feature, significant power
savings can be realized for combinatorial or sequential
operations when the inputs or clock change at a modest
rate. See Figure 6.
When the PEEL18LV8Z is powered up, a built-in feature
holds the outputs in tri-state until Vcc reaches 2.2V. This
prevents output transitions during power-up.
Figure 5 - Equivalent Circuits for the twelve configurations of the PEEL18LV8Z I/O Macrocell
Configuration
#
1
2
3
4
5
6
7
8
9
10
11
12
A
0
1
0
1
0
1
0
1
0
1
0
1
B
0
0
1
1
0
0
1
1
0
0
1
1
C
1
1
0
0
1
1
1
1
0
0
1
1
D
0
0
0
0
1
1
1
1
0
0
0
0
Input/Feedback Select
Register
Bi-directional I/O
Combinatorial
Register
Combinatorial Feedback
Combinatorial
Register
Register Feedback
Combinatorial
Output Select
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Active Low
Active High
Anachip Corp.
www.anachip.com.tw
5/10
Rev. 1.0 Dec 16, 2004
ANACHIP [ ANACHIP CORP ]
