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PEEL18LV8ZJ-25L 参数 Datasheet PDF下载

PEEL18LV8ZJ-25L图片预览
型号: PEEL18LV8ZJ-25L
PDF下载: 下载PDF文件 查看货源
内容描述: CMOS可编程电可擦除逻辑器件 [CMOS Programmable Electrically Erasable Logic Device]
分类和应用: 可编程逻辑器件时钟
文件页数/大小: 10 页 / 260 K
品牌: ANACHIP [ ANACHIP CORP ]
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Table 4 - A.C. Electrical Characteristics  
Over the operating range9  
-25  
I-35  
3V±10% 3.3V±10% 3V±10% 3.3V±10%  
Symbol  
Parameter  
Units  
Min Max Min Max Min Max Min Max  
tPD  
tOE  
Input6 to non-registered output in continuous mode13  
Input6 to output enable7  
30  
30  
30  
20  
25  
25  
25  
15  
40  
40  
40  
28  
35  
35  
35  
25  
ns  
ns  
ns  
ns  
tOD  
Input6 to output disable7  
tCO1  
Clock to Output  
Clock to comb output delay via internal registered  
tCO2  
40  
14  
35  
9
56  
20  
49  
13  
ns  
feedback  
tCF  
tSC  
Clock to Feedback  
ns  
ns  
Input6 or feedback setup to clock  
Input6 hold after clock  
20  
0
15  
0
28  
0
21  
0
tHC  
ns  
tCL, tCH  
tCP  
Clock low time, clock high time9  
Min clock period Ext (tSC + tCO1 )  
Internal feedback 1/ (tSC + tCF) 12  
External Feedback (1/ tCP) 12  
No Feedback 1/ (tCL + tCH) 12  
Asynchronous Reset Pulse Width  
Input to Asynchronous Reset  
20  
40  
29.4  
25  
25  
30  
13  
28  
18  
ns  
30  
56  
39  
ns  
fMAX1  
fMAX2  
fMAX3  
tAW  
41.6  
33.3  
38.4  
25  
20.8  
17.9  
17.9  
40  
29.4  
25.6  
27.7  
35  
MHz  
MHz  
MHz  
ns  
tAP  
30  
30  
5
25  
25  
5
40  
40  
5
35  
35  
5
ns  
tAR  
Asynchronous Reset recovery time  
Power-on reset time for registers in clear state14  
ns  
tRESET  
µs  
Inputs I/O,  
Registered Feedback,  
Synchronous Preset  
Clock  
Asynchronous  
Reset  
Registered  
Outputs  
Combinatorial  
Outputs  
Figure 7 - Switching Waveforms  
Notes:  
1.  
Minimum DC input is -0.5V, however, inputs may undershoot to  
-2.0V for periods less than 20 ns.  
8.  
9.  
Capacitances are tested on a sample basis.  
Test conditions assume: signal transition times of 3ns or less  
from the 10% and 90% points, timing reference levels of 1.5V  
(Unless otherwise specified).  
2.  
3.  
VI and VO are not specified for program / verify operation.  
The Supply Voltage range of 2.7 to 3.6V was chosen to allow  
this part to be used in both 3V ±10% and 3.3V ±10%  
applications.  
10.  
11.  
Test one output at a time for duration of less than 1 second.  
ICC for a typical application: This parameter is tested with the  
device programmed as an 8-bit Counter.  
4.  
Test Points for Clock and VCC in tR and tF are referenced at  
the 10% and 90% levels.  
12.  
Parameters are not 100% tested. Specifications are based on  
initial characterization and are tested after any design process  
modification that might affect operational frequency.  
tPD , tOE , tOD , tCO , tSC , and tAP are approximately 5 ns.  
slower on the first transaction from sleep mode.  
All inputs at GND.  
5.  
6.  
7.  
I/O pins are 0V and VCC .  
"Input" refers to an input pin signal.  
13.  
14.  
tOE is measured from input transition to V REF± 0.1V, TOD is  
measured from input transition to VOH -0.1V or VOL +0.1V;  
VREF =VL.  
Anachip Corp.  
www.anachip.com.tw  
Rev. 1.0 Dec 16, 2004  
8/10