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AS8NVLC512K32QC-20XT 参数 Datasheet PDF下载

AS8NVLC512K32QC-20XT图片预览
型号: AS8NVLC512K32QC-20XT
PDF下载: 下载PDF文件 查看货源
内容描述: 512K ×32模块的nvSRAM 3.3V高速SRAM与非易失性存储 [512K x 32 Module nvSRAM 3.3V High Speed SRAM with Non-Volatile Storage]
分类和应用: 存储静态存储器
文件页数/大小: 17 页 / 362 K
品牌: AUSTIN [ AUSTIN SEMICONDUCTOR ]
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AUSTIN SEMICONDUCTOR, INC.
ADVANCE INFORMATION
Austin Semiconductor, Inc.
AC Switching Characteristics
Parameters
Austin Semi
Alt
Parameters Parameters
Description
SRAM Read Cycle
t
ACE
t
ACS
Chip Enable Access Time
t
RC
t
AA
13
14
AS8nvLC512K32
45 ns
Min
Max
45
45
25
12
45
20
2
2
10
15
0
10
15
0
25
12
45
20
0
10
15
45
30
30
15
0
30
0
0
10
15
2
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
nvSRAM
20 ns
Min
Max
20
20
20
10
2
2
8
0
8
0
20
10
0
8
20
15
15
8
0
15
0
0
8
2
15
2
20
25
20
20
10
0
20
0
0
0
0
0
2
2
25
Min
25 ns
Max
25
t
RC
t
AA
t
OE
t
OH
t
LZ
t
HZ
t
OLZ
t
OHZ
t
PA
t
PS
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Active
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Byte Enable to Data Valid
Byte Enable to Output Active
Byte Disable to Output Inactive
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to End of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
Byte Enable to End of Write
t
DOE
t
OHA
t
LZCE
t
HZCE
t
HZOE
t
PU
t
PD
12
12
14
12, 15
12, 15
t
LZOE 12, 15
12, 15
t
DBE
t
LZBE
t
HZBE
12
12
SRAM Write Cycle
t
WC
t
WC
t
PWE
t
SCE
t
SD
t
HD
t
AW
t
SA
t
HA
t
HZWE
t
LZWE
t
BW
12, 15, 16
12, 15
t
WP
t
CW
t
DW
t
DH
t
AW
t
AS
t
WR
t
WZ
t
OW
Switching Waveforms
SRAM Read Cycle #1: Address Controlled
13, 14, 17
t
RC
Address
Address Valid
t
AA
Data Output
Previous Data Valid
t
OHA
Notes
13.WE\ must be HIGH during SRAM read cycles.
14. Device is continuously selected with CE\, OE\ LOW.
15.Measured ±200 mV from steady state output voltage.
16. If WE\ is LOW when CE\ goes LOW, the outputs remain in the high impedance state.
17. HSB\ must remain HIGH during read and write cycles.
Output Data Valid
AS8nvLC512K32
Rev. 0.0 08/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
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