欢迎访问ic37.com |
会员登录 免费注册
发布采购

HCPL-0300 参数 Datasheet PDF下载

HCPL-0300图片预览
型号: HCPL-0300
PDF下载: 下载PDF文件 查看货源
内容描述: 8 MBd的低输入电流光耦 [8 MBd Low Input Current Optocoupler]
分类和应用: 光电输出元件
文件页数/大小: 14 页 / 301 K
品牌: AVAGO [ AVAGO TECHNOLOGIES LIMITED ]
 浏览型号HCPL-0300的Datasheet PDF文件第4页浏览型号HCPL-0300的Datasheet PDF文件第5页浏览型号HCPL-0300的Datasheet PDF文件第6页浏览型号HCPL-0300的Datasheet PDF文件第7页浏览型号HCPL-0300的Datasheet PDF文件第9页浏览型号HCPL-0300的Datasheet PDF文件第10页浏览型号HCPL-0300的Datasheet PDF文件第11页浏览型号HCPL-0300的Datasheet PDF文件第12页  
Package Characteristics  
For -40°C ≤TA ≤85°C, unless otherwise specified. All typicals at TA = 25°C.  
Parameter  
Symbol Min.  
Typ.  
Max.  
Units Test Conditions  
Fig.  
Notes  
Input-Output Momentary  
Withstand Voltage*  
VISO  
3750  
V rms  
RH ≤ 50%, t = 1 min,  
3, 9  
TA = 25°C  
VI-O = 500 V  
f = 1 MHz  
Resistance, Input-Output  
Capacitance, Input-Output  
RI-O  
CI-O  
1012  
0.6  
3
3
pF  
*The Input-Output MomentaryWithstandVoltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage  
rating. For the continuous voltage rating refer to the IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Table (if applicable), your equipment level  
safety specification, or Avago Application Note 1074, “Optocoupler Input-Output Endurance Voltage.”  
Notes:  
5. The tPHL propagation delay is measured from the 50% point on the  
leading edge of the input pulse to the 1.5 V point on the leading  
edge of the output pulse.  
6. CMH is the maximum tolerable rate of rise of the common mode  
voltage to assure that the output will remain in a high logic state  
(i.e., VOUT > 2.0V).  
1. Bypassing the power supply line is required with a 0.1 µF ceramic  
disc capacitor adjacent to each optocoupler as illustrated in Figure  
19. The power supply bus for the optocoupler(s) should be separate  
from the bus for any active loads, otherwise a larger value of bypass  
capacitor (up to 0.5µF) may be needed to suppress regenerative  
feedback via the power supply.  
2. Peaking circuits may produce transient input currents up to 100  
mA, 500 ns maximum pulse width, provided average current does  
not exceed 5 mA.  
7. CML is the maximum tolerable rate of fall of the common mode  
voltage to assure that the output will remain in a low logic state  
(i.e., VOUT < 0.8 V).  
3. Device considered a two terminal device: pins 1, 2, 3, and 4 shorted  
together, and pins 5, 6, 7, and 8 shorted together.  
4. The tPLH propagation delay is measured from the 50% point on the  
trailing edge of the input pulse to the 1.5 V point on the trailing  
edge of the output pulse.  
8. CP is the peaking capacitance. Refer to test circuit in Figure 8.  
9. In accordance with UL 1577, each optocoupler is momentary with-  
stand proof tested by applying an insulation test voltage ≥4500  
Vrms for 1 second (leakage detection current limit, II-O 5 µA). This  
test is performed before the 100% production test for partial dis-  
charge (Method b) shown in the IEC/EN/DIN EN 60747-5-2 Insula-  
tion Characteristics Table, if applicable.  
Figure 2. Typical input diode forward charac-  
teristics.  
Figure 3. Typical output voltage vs. forward  
input current vs. temperature.  
Figure 4. Typical logic high output current vs.  
temperature.  
8