EXTERNAL RESET
POWER-ON RESET
The PCM3000 and PCM3001 include a reset input, RSTB
(pin 28). As shown in Figure 8, the external reset signal must
drive RSTB low for a minimum of 40 nanoseconds while
system clock is active in order to initiate the reset sequence.
Initialization starts on the rising edge of RSTB, and requires
1024 system clock cycles for completion. Figure 10 shows
the state of the DAC and ADC outputs during and after the
reset sequence.
Both the PCM3000 and PCM3001 have internal power-on
reset circuitry. Power-on reset occurs when system clock
(XTI or CLKIO) is active and VDD > 4.0V. For the PCM3001,
the system clock must complete a minimum of 3 complete
cycles prior to VDD > 4.0V to ensure proper reset operation.
The initialization sequence requires 1024 system cycles for
completion, as shown in Figure 7. Figure 10 shows the state
of the DAC and ADC outputs during and after the reset
sequence.
4.4V
4.0V
3.6V
VDD
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
(XTI or CLKIO)
FIGURE 7. Internal Power-On Reset Timing.
tRST = 40ns minimum
RSTB
tRST
Reset
Reset Removal
Internal Reset
1024 System Clock Periods
System Clock
(XTI or CLKIO)
FIGURE 8. External Forced Reset Timing.
ML
MC
MD
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
FIGURE 9. Control Data Input Format.
®
14
PCM3000/3001
BB [ BURR-BROWN CORPORATION ]
