to LRCIN. Internal operation of the ADC will also stop with
1/fS, and the digital output codes will be set to bipolar zero
until re-synchronization occurs. If LRCIN is synchronized
with 5 or less bit clocks to the system clock, operation will be
normal.
SYNCHRONIZATION WITH THE DIGITAL
AUDIO SYSTEM
PCM3000/3001 operates with LRCIN synchronized to the
system clock. The CODEC does not require any specific
phase relationship between LRCIN and the system clock, but
there must be synchronization. If the synchronization be-
tween the system clock and LRCIN changes more than 6 bit
clocks (BCKIN) during one sample (LRCIN) period because
of phase jitter on LRCIN, internal operation of the DAC will
stop within 1/fS, and the analog output will be forced to
bipolar zero (VCC/2) until the system clock is re-synchronized
Figure 11 illustrates the effects on the output when synchro-
nization is lost. Before the outputs are forced to bipolar zero
(<1/fS seconds), the outputs are not defined and some noise
may occur. During the transitions between normal data and
undefined states, the output has discontinuities, which will
cause output noise.
Reset Removal or Power-Down(1) OFF
Internal Reset
DAC VOUT
Reset
32/fS
VCOM
(= 1/2 x VCC2)
4096/fS
(2)
Zero
ADC DOUT
NOTES: (1) Power-Down is for PCM3000 only. (2) The HPF transient response
(exponentially attenuationed signal with 200ms time constant) appears intially.
FIGURE 10. DAC Output and ADC Output for Reset and Power-Down.
State of
Synchronization
Synchronous
Asynchronous
Synchronous
within
1/fS
22.2/fS
Undefined Data
VCOM
(= 1/2 x VCC2)
Undefined
Data
DAC VOUT
Normal
Normal
32/fS
Undefined Data
Normal(1)
Normal
ADC DOUT
ZERO
NOTE: (1) The HPF transient response (exponentially attenuationed signal with 200ms time constant) appears initally.
FIGURE 11. DAC Output and ADC Output When Synchronization is Lost.
®
15
PCM3000/3001
BB [ BURR-BROWN CORPORATION ]
