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BS62LV4007TC-70 参数 Datasheet PDF下载

BS62LV4007TC-70图片预览
型号: BS62LV4007TC-70
PDF下载: 下载PDF文件 查看货源
内容描述: 非常低的功率/电压CMOS SRAM 512K ×8位 [Very Low Power/Voltage CMOS SRAM 512K X 8 bit]
分类和应用: 静态存储器
文件页数/大小: 10 页 / 374 K
品牌: BSI [ BRILLIANCE SEMICONDUCTOR ]
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BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
BS62LV4007
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
MIN.
TYP.
MAX.
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN.
TYP. MAX.
UNIT
t
AVAX
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
55
--
--
--
10
10
--
--
10
--
--
--
--
--
--
--
--
--
--
55
55
30
--
--
30
25
--
70
--
--
--
10
10
--
--
10
--
--
--
--
--
--
--
--
--
--
70
70
35
--
--
35
30
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
R0201-BS62LV4007
4
Revision 1.1
Jan.
2004