BSI
WRITE CYCLE2
(1,6)
BS62LV8006
t
WC
ADDRESS
CE2
(11)
CE1
(5)
t
CW
t
WE
AW
t
WP
t
WR
(3)
(2)
t
AS
(4,10)
t
WHZ
D
OUT
t
OW
t
DW
t
DH
(8,9)
(7)
(8)
D
IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. T
WR
is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. T
CW
is measured from the later of CE2 going high or CE1 going low to the end of write.
R0201-BS62LV8006
7
Revision 2.1
Jan.
2004
BSI [ BRILLIANCE SEMICONDUCTOR ]
