CAT25C128/256
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (7FFFh for 25C256 and 3FFFh for 25C128) is
reached, the address counter rolls over to 0000h allow-
ing the read cycle to be continued indefinitely. The read
operation is terminated by pulling the
CS
high. To read
the status register, RDSR instruction should be sent.
The contents of the status register are shifted out on the
SO line. The status register may be read at any time
even during a write cycle.Read sequence is illustrated in
figure 4. Reading status register is illustrated in figure 5.
DEVICE OPERATION
Write Enable and Disable
The CAT25C128/256 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when V
cc
is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling
CS
low. The 8-bit read
instruction is transmitted to the CAT25C128/256, fol-
lowed by the 16-bit address (the Most Significant Bit is
don’t care for 25C256 and the two most significant bits
are don't care for the 25C128).
Figure 2. WREN Instruction Timing
CS
SK
SI
0
0
0
0
0
1
1
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
Figure 3. WRDI Instruction Timing
CS
SK
SI
0
0
0
0
0
1
0
0
SO
Note: Dashed Line= mode (1, 1) — — — —
HIGH IMPEDANCE
7
Doc. No. 25088-00 1/01
CATALYST [ CATALYST SEMICONDUCTOR ]
