CAT25C128/256
address will remain constant.The only restriction is that
the 64 bytes must reside on the same page. If the
address counter reaches the end of the page and clock
continues, the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written. The CAT25C128/256 is automatically returned
to the write disable state at the completion of the write
cycle. Figure 8 illustrates the page write sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
The CAT25C128/256 features page write capability.
After the initial byte the host may continue to write up to
64 bytes of data to the CAT25C128/256. After each byte
of data is received, six lower order address bits are
internally incremented by one; the high order bits of
Figure 6. Write Instruction Timing
CS
0
SK
OPCODE
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
29
30
31
DATA IN
SI
0
0
0
0
0
0
1
0
ADDRESS
D7 D6 D5 D4 D3 D2 D1 D0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
Figure 7. WRSR Timing
CS
0
SCK
OPCODE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DATA IN
SI
0
0
0
0
0
0
0
1
7
MSB
6
5
4
3
2
1
0
SO
HIGH IMPEDANCE
Note: Dashed Line= mode (1, 1) — — — —
Figure 8. Page Write Instruction Timing
CS
0
SK
1
2
3
4
5
6
7
8
21
22
23 24-31
32-39
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
OPCODE
DATA IN
SI
0
0
0
0
0
0
1
0
ADDRESS
Data
Byte 1
Data
Byte 2
Data
Byte 3
Data Byte N
0
7..1
SO
Note: Dashed Line= mode (1, 1) — — — —
HIGH IMPEDANCE
9
Doc. No. 25088-00 1/01
CATALYST [ CATALYST SEMICONDUCTOR ]
