CAT28LV256
Figure 1. A.C. Testing Input/Output Waveform
(2)
VCC - 0.3V
INPUT PULSE LEVELS
0.0 V
0.6 V
28LV256 F04
2.0 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
V
cc
1.8K
DEVICE
UNDER
TEST
1.3K
OUTPUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
28LV256 F05
A.C. CHARACTERISTICS, Write Cycle
V
CC
= 3.0V to 3.6V, unless otherwise specified
28LV256-20
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW(3)
t
OES
t
OEH
t
WP(3)
t
DS
t
DH
t
INIT(1)
t
BLC(1)(4)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE
Setup Time
CE
Hold Time
CE
Pulse Time
OE
Setup Time
OE
Hold Time
WE
Pulse Width
Data Setup Time
Data Hold Time
Write Inhibit Period After Power-up
Byte Load Cycle Time
0
100
0
0
150
0
0
150
50
0
5
0.15
10
100
Min.
Max.
10
28LV256-25
Min.
Max.
10
0
100
0
0
150
0
0
150
50
0
5
0.15
10
100
28LV256-30
Min.
Max. Units
10
0
100
0
0
150
0
0
150
50
0
5
0.15
10
100
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
BLC
max. begins with every LOW to HIGH transition of
WE.
If allowed to time out, a page or byte write will begin;
however a transition from HIGH to LOW within t
BLC
max. stops the timer.
5
Doc. No. 25040-00 4/01 P-1
CATALYST [ CATALYST SEMICONDUCTOR ]
