CAT28LV256
DEVICE OPERATION
Read
Data stored in the CAT28LV256 is transferred to the
data bus when
WE
is held high, and both
OE
and
CE
are
held low. The data bus is set to a high impedance state
when either
CE
or
OE
goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Byte Write
A write cycle is executed when both
CE
and
WE
are low,
and
OE
is high. Write cycles can be initiated using either
WE
or
CE,
with the address input being latched on the
falling edge of
WE
or
CE,
whichever occurs last. Data,
conversely, is latched on the rising edge of
WE
or
CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Figure 3. Read Cycle
tRC
ADDRESS
tCE
CE
tOE
OE
VIH
WE
tLZ
tOLZ
DATA OUT
HIGH-Z
tOH
DATA VALID
tAA
28LV256 F06
tOHZ
tHZ
DATA VALID
Figure 4. Byte Write Cycle [WE Controlled]
WE
ADDRESS
tAS
tCS
CE
tAH
tCH
tWC
OE
tOES
WE
tBLC
DATA OUT
HIGH-Z
tWP
tOEH
DATA IN
DATA VALID
tDS
tDH
28LV256 F07
Doc. No. 25040-00 4/01 P-1
6
CATALYST [ CATALYST SEMICONDUCTOR ]
