CS4351-CZZ 参数 Datasheet PDF下载

CS4351

4.2

System Clocking

The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)

clocks. The left/right clock, defined also as the input sample rate (F

s

), must be synchronously derived from

the MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several stan-

dard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6.

Refer to section 4.3 for the required SCLK timing associated with the selected Digital Interface Format,

and

clock frequencies.

Sample Rate

(kHz)

32

44.1

48

MCLK (MHz)

512x

768x

16.3840

24.5760

22.5792

33.8688

24.5760

36.8640

256x

8.1920

11.2896

12.2880

384x

12.2880

16.9344

18.4320

1024x

32.7680

45.1584

49.1520

1152x

36.8640

Table 4. Single-Speed Mode Standard Frequencies

Sample Rate

(kHz)

64

88.2

96

MCLK (MHz)

256x

16.3840

22.5792

24.5760

128x

8.1920

11.2896

12.2880

192x

12.2880

16.9344

18.4320

384x

24.5760

33.8688

36.8640

512x

32.7680

45.1584

49.1520

Table 5. Double-Speed Mode Standard Frequencies

Sample Rate

(kHz)

176.4

192

MCLK (MHz)

128x

22.5792

24.5760

64x

11.2896

12.2880

96x

16.9344

18.4320

192x

33.8688

36.8640

256x

45.1584

49.1520

Table 6. Quad-Speed Mode Standard Frequencies

= Denotes clock modes which are NOT auto detected

DS566PP2

17