CS4351-CZZ 参数 Datasheet PDF下载

CS4351

4.3

Digital Interface Format

The device will accept audio samples in 1 of 4 digital interface formats in Stand-Alone mode, as illustrated

in Table 7, and 1 of 6 formats in Control Port mode, as illustrated in Table 8.

4.3.1

Stand-Alone Mode

The desired format is selected via the DIF1 and DIF0 pins. For an illustration of the required rela-

tionship between the LRCK, SCLK and SDIN, see Figures 5-7. For all formats, SDIN is valid on

the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in format 2,

and 48 cycles per LRCK period in format 3.

DIF0

0

0

1

1

DIF1

0

1

0

1

I S, up to 24-bit Data

Left Justified, up to 24-bit Data

Right Justified, 24-bit Data

Right Justified, 16-bit Data

2

DESCRIPTION

FORMAT

0

1

2

3

FIGURE

Table 7. Digital Interface Format - Stand-Alone Mode

4.3.2

Control Port Mode

The desired format is selected via the DIF2, DIF1 and DIF0 bits in the Mode Control 2 register (see

section 6.2.1) . For an illustration of the required relationship between LRCK, SCLK and SDIN,

see Figures 5-7. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have

at least 32 cycles per LRCK period in format 2, 48 cycles in format 3, 40 cycles in format 4, and

36 cycles in format 5.

LR C K

L e ft C h a n n e l

R ig h t C h a n n e l

SCLK

S D IN

MSB

-1 -2 -3 -4 -5

+5 +4 +3 +2 +1

LSB

M SB

-1 -2 -3 -4

+5 +4 +3 +2 +1

LS B

Figure 5. Left Justified up to 24-Bit Data

LR CK

L e ft C h a n n e l

R ig h t C h a n n e l

SCLK

S D IN

M SB

-1 -2 -3 -4 -5

+5 +4 +3 +2 +1

LSB

M SB

-1 -2 -3 -4

+5 +4 +3 +2 +1

LSB

Figure 6. I

2

S, up to 24-Bit Data

LR C K

L e ft C h a n ne l

R ig h t C h a n n e l

SC LK

SD IN

M SB

MSB

+1 +2 +3 +4 +5

-7 -6 -5 -4 -3 -2 -1

LS B

MSB

+1 +2 +3 +4 +5

-7 -6 -5 -4 -3 -2 -1

LS B

Figure 7. Right Justified Data

18

DS566PP2