CS5451A
1.
PIN DESCRIPTION
Serial Clock Output
Serial Data Output
Frame Sync
Serial Port Enable
Current Input Gain
Analog Ground
Reference Input
Positive Analog Supply
Negative Analog Supply
Differential Voltage Input 3
Differential Voltage Input 3
Differential Current Input 3
Differential Current Input 3
SCLK
SDO
FSO
SE
GAIN
AGND
VREFIN
VA+
VA -
VIN3+
VIN3-
IIN3+
IIN3-
1
2
3
4
6
7
8
9
10
11
12
13
14
28
27
26
25
VD+
DGND
CPD
XIN
Digital Supply
Digital Ground
Charge Pump Drive
Master Clock
CS5451A
5
24
23
22
21
20
19
18
17
16
15
RESET
Reset
OWRS
Output Word Rate Select
VIN1+
VIN1-
IIN1+
IIN1-
VIN2+
VIN2-
IIN2+
IIN2-
Differential Voltage Input 1
Differential Voltage Input 1
Differential Current Input 1
Differential Current Input 1
Differential Voltage Input 2
Differential Voltage Input 2
Differential Current Input 2
Differential Current Input 2
Reference Output
VREFOUT
Clock Generator
Master Clock Input
Control Pins and Serial Data I/O
Serial Clock Output
Serial Data Output
Frame Sync
Serial Port Enable
Current Input Gain
Output Word Rate Select
23
Reset
Analog Inputs/Outputs
Voltage Reference Input
Voltage Reference Output
Differential Voltage Inputs
7
8
VREFIN
- The input to this pin establishes the voltage reference for the on-chip modulator.
VREFOUT
- The on-chip voltage reference output. The voltage reference has a nominal magni-
tude of 1.2 V and is referenced to the AGND pin on the converter.
25
XIN
- External clock signal or oscillator input.
1
2
3
4
5
SCLK
- Serial port clock signal that determines the output data rate for SDO pin. Rate of SCLK is
dependent on the XIN frequency and state of OWRS pin.
SDO
-Serial port data output pin. Data will be output at a rate defined by SCLK.
FSO
- Framing signal indicates when data samples are about to be transmitted on the SDO pin.
SE
- When SE is low, the output pins of the serial port are tri-stated.
GAIN
- A logic high sets current channel gain to 1, a logic low sets the gain to 20. If no connection
is made to this pin, it will default to logic low level (through internal 200 kΩ resistor to DGND).
OWRS
- A logic low sets the output word rate (OWR) to XIN/2048 (Hz). A logic high sets the
OWR to XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low
level (through internal 200 kΩ resistor to DGND).
RESET
- Low activates Reset, all internal registers are set to their default states.
24
11,12
VIN3+, VIN3-
- Differential analog input pins for the voltage channel 3.
18,17
VIN2+, VIN2-
- Differential analog input pins for the voltage channel 2.
22,21
VIN1+, VIN1-
- Differential analog input pins for the voltage channel 1.
13,14
IIN3+, IIN3-
- Differential analog input pins for the current channel 3.
16,15
IIN2+, IIN2-
- Differential analog input pins for the current channel 2.
20,19
IIN1+, IIN1-
- Differential analog input pins for the current channel 1.
Differential Current Inputs
Power Supply Connections
Analog Ground
Positive Analog Supply
Negative Analog Supply
Charge Pump Drive
Digital Ground
Positive Digital Supply
6
9
10
AGND
- Analog ground.
VA+
- The positive analog supply. Typical +3 V ±10% relative to AGND.
VA-
- The negative analog supply. Typical -2 V ±10% relative to AGND.
CPD
- Designed to drive external charge pump circuitry that will produce a negative analog sup-
ply (VA-)voltage.
DGND
- Digital Ground.
VD+
- The positive digital supply. Typical +3 V ±10% relative to AGND.
26
27
28
DS635F2
3
CIRRUS [ CIRRUS LOGIC ]
