CS5451A
ANALOG CHARACTERISTICS (continued)
Parameter
Symbol
Min
Typ
Max
Unit
Power Supplies
Power Supply Currents
Typical VA+ = VD+ = +3 V; VA- = -2 V
I
A+
with CPD
PSCA
PSCD
PSCD
-
-
-
4.0
5.0
1.0
5.3
6.3
1.5
mA
mA
mA
I
D+
I
without CPD
With CPD
D+
Power Consumption
(Note 2)
PC
PC
-
-
27
23
35
31
mW
mW
Without CPD
Power Supply Rejection
50, 60 Hz (Note 3)
50, 60 Hz (Note 3)
(DC)
Voltage Channel
Current Channel
PSRR
PSRR
PSRR
50
50
60
-
65
90
-
-
-
dB
dB
dB
Notes: 1. Specifications for Gain = 20 apply only to Current Channels. Voltage Channels are fixed to Gain = 1
2. All outputs unloaded. All inputs CMOS level.
3. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3 V, AGND = DGND = 0 V, VA- = -2 V (using charge-
pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins.
The “+” and “-” input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words
are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this
rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied
at the channel’s inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq.
PSRR is then (in dB):
⎧
⎨
⎩
⎫
⎬
⎭
106.07
-----------------
PSRR = 20 ⋅ log
DIGITAL CHARACTERISTICS (See Note 4)
V
eq
•
•
•
•
Min/Max characteristics and specifications are guaranteed over all Operating Conditions.
Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.
VA+ = VD+ = 3V ±10%; VA- = -2 V ±10%; AGND = DGND = 0 V. All voltages with respect to 0 V.
XIN = 4.096 MHz
Parameter
Master Clock Characteristics
Symbol
Min
Typ
Max
Unit
Master Clock Frequency
Master Clock Duty Cycle
Filter Characteristics
XIN
3
4.096
-
5
MHz
%
40
60
High Rate Filter Output Word Rate
OWRS = 0 OWR
OWRS = 1 OWR
-
-
XIN/2048
XIN/1024
-
-
Hz
Hz
Input/Output Characteristics
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
V
0.6 VD+
0.0
-
-
-
VD+
0.8
-
V
V
V
IH
V
IL
I
= -5.0 mA
= 5.0 mA
(Note 5)
V
(VD+) - 1.0
out
OH
Low-Level Output Voltage
I
V
I
-
-
-
-
-
±1
-
0.4
±10
±10
-
V
out
OL
Input Leakage Current
µA
µA
pF
in
3-State Leakage Current
Digital Output Pin Capacitance
I
OZ
C
9
out
Notes: 4. All measurements performed under static conditions.
5. For OWRS and GAIN pins, input leakage current is 30 µA (Max).
DS635F2
5
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