CS5460A
1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS
(T
A
= -40 °C to +85 °C; VA+ = VD+ = +5 V ±10%; VREFIN = +2.5 V; VA- = AGND = 0 V; MCLK = 4.096 MHz,
K = 1; N = 4000 ==> OWR = 4000 Sps.)(See Notes 1, 2, 3, 4, and 5.)
Parameter
Symbol
(DC, 50, 60 Hz)
CMRR
Min
80
-
(Gain = 10)
(Gain = 50)
I
IN
THD
I
(Gain = 10 or 50)
(50, 60 Hz)
(Gain = 10)
(Gain = 50)
(Note 6)
(Gain = 10)
(Gain = 50)
(Gain = 10)
(Gain = 50)
(Note 1)
(Note 1)
{(V
VIN+
) - (V
VIN-
)}
VOS
I
FSE
I
V
IN
THD
V
(50, 60 Hz)
C
inV
(Note 6)
Z
inV
C
in
-
-
80
-0.25
-
-
-
-
-
-
-
-
-
-
62
VA-
-
-
-
-
(Note 1)
(Note 1)
VOS
V
FSE
V
-
-
Typ
-
5
-
-
-
-
-
25
25
30
30
-
-
±0.001
±0.001
-
-
-
-
0.2
5
-
±0.01
±0.01
Max
-
-
500
100
-
VA+
-115
-
-
-
-
20
4
-
-
500
-
VA+
-70
-
-
250
-
-
Unit
dB
nV/°C
mV
P-P
mV
P-P
dB
V
dB
pF
pF
kΩ
kΩ
µV
rms
µV
rms
%F.S.
%F.S.
mV
P-P
dB
V
dB
pF
MΩ
µV
rms
%F.S.
%F.S.
Accuracy (Both Channels)
Common Mode Rejection
Offset Drift (Without the High Pass Filter)
Analog Inputs (Current Channel)
Maximum Differential Input Voltage Range
{(V
IIN+
) - (V
IIN-
)}
Total Harmonic Distortion
Common Mode + Signal on IIN+ or IIN-
Input Capacitance
Effective Input Impedance
Crosstalk with Voltage Channel at Full Scale
Z
inI
Z
inI
Noise (Referred to Input)
Accuracy (Current Channel)
Bipolar Offset Error
Full-Scale Error
Analog Inputs (Voltage Channel)
Maximum Differential Input Voltage Range
Total Harmonic Distortion
Common Mode + Signal on VIN+ or VIN-
Crosstalk with Current Channel at Full Scale
Input Capacitance
Effective Input Impedance
Noise (Referred to Input)
Accuracy (Voltage Channel)
Bipolar Offset Error
Full-Scale Error
Notes:
1. Bipolar Offset Errors and Full-Scale Gain Errors for the current and voltage channels refer to the respective Irms
Register and Vrms Register output, when the device is operating in ‘continuous computation cycles’ data acquisition
mode,
after
offset/gain system calibration sequences have been executed. These specs do
not
apply to the error
of the Instantaneous Current/Voltage Register output.
Specifications guaranteed by design, characterization, and/or test.
Analog signals are relative to VA- and digital signals to DGND unless otherwise noted.
In requiring VA+ = VD+ =5 V ±10%, note that it is allowable for VA+, VD+ to differ by as much as ±200 mV, as long
as VA+ > VD+.
Note that “Sps” is an abbreviation for units of “samples per second”.
Effective Input Impedance (Zin) is determined by clock frequency (DCLK) and Input Capacitance (IC).
Zin = 1/(IC*DCLK/4). Note that DCLK = MCLK / K.
2.
3.
4.
5.
6.
5
CIRRUS [ CIRRUS LOGIC ]
