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CS5460A-BS 参数 Datasheet PDF下载

CS5460A-BS图片预览
型号: CS5460A-BS
PDF下载: 下载PDF文件 查看货源
内容描述: 单相双向功率/电能IC [Single Phase Bi-Directional Power/Energy IC]
分类和应用:
文件页数/大小: 54 页 / 879 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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CS5460A
SWITCHING CHARACTERISTICS
(T
A
= -40 °C to +85 °C; VA+ = 5.0 V ±10%; VD+ = 3.0 V ±10% or 5.0 V ±10%; VA- = 0.0 V; Logic Levels:
Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50 pF))
Parameter
Master Clock FrequencyCrystal/Internal Gate Oscillator (Note 24)
Master Clock Duty Cycle
CPUCLK Duty Cycle
(Note 25)
Rise Times
Any Digital Input Except SCLK (Note 26)
SCLK
Any Digital Output
Fall Times
Any Digital Input Except SCLK (Note 26)
SCLK
Any Digital Output
Start-up
Oscillator Start-Up Time
XTAL = 4.096 MHz (Note 27)
Symbol
MCLK
Min
2.5
40
40
-
-
-
-
-
-
-
-
200
200
50
50
100
100
-
-
-
Typ
4.096
-
-
-
50
-
-
50
60
-
-
-
-
-
-
-
20
20
20
8
8
50
48
100
50
100
8
16
Max
20
60
60
1.0
100
-
1.0
100
-
-
2
-
-
-
-
-
-
50
50
50
Unit
MHz
%
%
µs
µs
ns
µs
µs
ns
ms
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MCLK
MCLK
ns
MCLK
MCLK
MCLK
ns
ns
t
rise
t
fall
t
ost
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Serial Port Timing
Serial Clock Frequency
Serial Clock
SDI Timing
CS Falling to SCLK Rising
Data Set-up Time Prior to SCLK Rising
Data Hold Time After SCLK Rising
SCLK Falling Prior to CS Disable
Pulse Width High
Pulse Width Low
SDO Timing
CS Falling to SDI Driving
SCLK Falling to New Data Bit
CS Rising to SDO Hi-Z
Auto-Boot Timing
Serial Clock
MODE setup time to RESET Rising
RESET rising to CS falling
CS falling to SCLK rising
SCLK falling to CS rising
Pulse Width High
Pulse Width Low
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
CS rising to driving MODE low (to end auto-boot sequence).
SDO guaranteed setup time to SCLK rising
Notes: 24. Device parameters are specified with a 4.096 MHz clock, yet, clocks between 3 MHz to 20 MHz can be
used. However, for input frequencies over 5 MHz, an external oscillator must be used.
25. If external MCLK is used, then duty cycle must be between 45% and 55% to maintain this specification.
26. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
27. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an
external clock source.
9