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CS61584A-IQ3Z 参数 Datasheet PDF下载

CS61584A-IQ3Z图片预览
型号: CS61584A-IQ3Z
PDF下载: 下载PDF文件 查看货源
内容描述: 双T1 / E1线路接口 [DUAL T1/E1 LINE INTERFACE]
分类和应用: 数字传输接口电信集成电路电信电路PC
文件页数/大小: 54 页 / 1013 K
品牌: CIRRUS [ CIRRUS LOGIC ]
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DS261PP5
CS61584A
ANALOG CHARACTERISTICS
(T
A
= -40 to 85 °C; power supply pins within ±5% of nominal.)
Parameter
Symbol
Min
-
-
-
60
55
45
40
160
300
6.0
0.4
12
18
14
Typ
20
-13.6
0.3
65
-
50
-
175
-
-
-
22
24
22
Max
-
-
-
70
75
55
60
190
-
-
-
dB
-
-
-
Hz
1.25
-
-
28
4.0
1.25
60
43
-
-
-
-
Unit
kΩ
dB
V
% of
Peak
(Note 7)
(Note 8)
T1, FCC Part 68 and E1 (Note
(Note 10)
Allowable Consecutive Zeros before LOS
Receiver Input Jitter Tolerance (DSX-1, E1)
10 Hz and below
(Note 11)
2 kHz
10 kHz - 100 kHz
Receiver Return Loss
(Notes 12, 13, and 14)
51 kHz - 102 kHz
102 kHz - 2.048 MHz
2.048 MHz - 3.072 MHz
Jitter Attenuator
Jitter Attenuator Corner Frequency
T1
(Notes 12 and 15)
E1
Attenuation at 10 kHz Jitter Frequency
(Notes 12 and 15)
Attenuator Input Jitter Tolerance
(Note 12)
(Before Onset of FIFO Overflow or Underflow Protection)
Transmitter
Arbitrary Pulse Amplitude at Transformer Secondary
T1, DSX-1
T1, DS1
E1, 75
E1, 120
Notes: 7. For input amplitude of 1.2 V
pk
to 4.14 V
pk
.
Receiver
RTIP/RRING Differential Input Impedance
Sensitivity Below DSX-1 (0 dB = 2.4 V)
Loss of Signal Threshold
Data Decision Threshold
T1, DSX-1
bits
UI
dB
UI
pk-pk
-
-
-
-
73
52
43
52
-
-
-
-
mV/LS
B
8. For input amplitude of 0.5 V
pk
to 1.2 V
pk
, and 4.14 V
pk
to 5.0 V
pk
.
9. For input amplitude of 1.07 V
pk
to 4.14 V
pk
.
10. For input amplitude of 4.14 V
pk
to 5.0 V
pk
.
11. Jitter tolerance increases at lower frequencies. Refer to the Receiver section.
12. Not production tested. Parameters guaranteed by design and characterization.
13. Typical performance using the line interface circuitry recommended in the Applications section.
14. Return loss = 20 log
10
ABS((z
1
+ z
0
) / (z
1
- z
0
)) where z
1
= impedance of the transmitter or receiver, and
z
0
= cable impedance.
15. Attenuation measured with sinusoidal input jitter equal to 3/4 of measured jitter tolerance. Circuit
attenuates jitter at 20 dB/decade above the corner frequency. Output jitter can increase significantly
when more than 28 UI's are input to the attenuator. The jitter attenuator -3 dB knee in T1 mode is
selectable for 4.0 Hz or 1.25 Hz. Refer to the Jitter Attenuator section.
6
DS261PP5
DS261F1