CS8420
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; C
L
= 20 pF.
Parameter
OSCLK Active Edge to SDOUT Output Valid
SDIN Setup Time Before ISCLK Active Edge
SDIN Hold Time After ISCLK Active Edge
Master Mode
O/RMCK to I/OSCLK active edge delay
O/RMCK to I/OLRCK delay
I/OSCLK and I/OLRCK Duty Cycle
Slave Mode
I/OSCLK Period
I/OSCLK Input Low Width
I/OSCLK Input High Width
I/OSCLK Active Edge to I/OLRCK Edge
(Note 7, 9, 11)
I/OLRCK Edge Setup Before I/OSCLK Active Edge
(Note 7, 9, 12)
t
lrcks
20
-
-
ns
t
sckw
t
sckl
t
sckh
t
lrckd
36
14
14
20
-
-
-
-
-
-
-
-
ns
ns
ns
ns
(Note 7, 8)
t
smd
t
lmd
0
0
-
-
-
50
16
17
-
ns
ns
%
Symbol
t
dpd
t
ds
t
dh
Min
-
20
20
Typ
-
-
-
Max
25
-
-
Units
ns
ns
ns
7. The active edges of ISCLK and OSCLK are programmable.
8. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its rising edge.
When these signals are derived from RMCK, they are clocked from its falling edge.
9. The polarity of ILRCK and OLRCK is programmable.
10. No more than 128 SCLK per frame.
11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
ISCLK
OSCLK
(output)
ILRCK
O LRCK
(output)
t sm d
t
RM CK
(output)
Hardware M ode
RM CK
(output)
Software M ode
O M CK
(input)
lm d
ILRCK
OLRCK
(input)
ISCLK
OSCLK
(input)
t
lrckd
t
lrcks
t
sckh
t
sckl
t
sckw
SDIN
t ds
SDOUT
t dh
t dpd
Figure 1. Audio Port Master Mode Timing
Figure 2. Audio Port Slave Mode and Data Input Timing
DS245F4
9
CIRRUS [ CIRRUS LOGIC ]
