EP9312
Universal Platform SOC Processor
IDE Interface
Register Transfers
Parameter
Cycle time
Address valid to DIORn / DIOWn setup
DIORn / DIOWn pulse width 8-bit
DIORn / DIOWn recovery time
DIOWn data setup
DIOWn data hold
DIORn data setup
DIORn data hold
DIORn data high impedance state
DIORn / DIOWn to address valid hold
Read Data Valid to IORDY
active (if IORDY initially low after t
A
)
IORDY Setup time
IORDY Pulse Width
IORDY assertion to release
DIOWn assert to data valid
Note:
(max)
(max)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(max)
(min)
(min)
(Note 4)
(Note 3, 4)
(Note 4)
(Note 2, 4)
(Note 4)
(Notes 1, 4, 5)
(Note 4)
(Note 1, 4)
(Note 1, 4)
(Note 4)
Symbol
t
0
t
1
t
2
t
2i
t
3
t
4
t
5
t
6
t
6z
t
9
t
RD
t
A
t
B
t
C
t
DDV
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4
(in ns) (in ns) (in ns) (in ns) (in ns)
600
70
290
-
60
0
20
0
30
20
0
35
1250
5
10
383
50
290
-
45
0
20
0
30
15
0
35
1250
5
10
330
30
290
-
30
0
20
0
30
10
0
35
1250
5
10
180
30
80
70
30
0
20
0
30
10
0
35
1250
5
10
120
25
70
25
20
0
20
0
30
10
0
35
1250
5
10
1. t
0
is the minimum total cycle time, t
2
is the minimum DIORn / DIOWn assertion time, and t
2i
is the minimum DIORn / DIOWn
negation time. A host implementation shall lengthen t
2
and/or t
2i
to ensure that t
0
is equal to or greater than the value
reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device.
3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host
shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at
the t
A
after the activation of DIORn or DIOWn, then t
5
shall be met and t
RD
is not applicable. If the device is driving IORDY
negated at the time t
A
after the activation of DIORn or DIOWn, then t
RD
shall be met and t
5
is not applicable.
4. Timings based upon software control. See User’s Guide.
5. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t
0
by utilizing the
16-bit PIO value.
6. All IDE timing is based upon HCLK = 100 MHz.
30
©
Copyright 2005 Cirrus Logic (All Rights Reserved)
DS515PP7
CIRRUS [ CIRRUS LOGIC ]
