4
4.0 Mechanical/Electrical Specifications
4.1 Timing Requirements
and
illustrate the timing requirements for the microprocessor
interface. The parameter t
cyc
is the period of the receive DS3/E3 clock (DS3CKI).
This clock signal is used in the read circuit of the microprocessor to ensuring no
status events are missed and that counter values are accurately read.
Read operation requires the read strobe to be low for three t
cyc
clock cycles
ensuring that changing status and error counts are properly processed. If a gapped
clock is applied to the circuit, it is sufficient to allow three receive clock cycles
between read strobes to allow a latching circuit to clear in the microprocessor
interface.
Table 4-1. Microprocessor Interface Timing
(1 of 2)
Symbol
t
as
t
cale
t
ah
t
rwa
t
adwrh
t
adrdl
t
wrw
(Read Operation)
t
wrw
(Write Operation)
t
rdd
t
rdh
Parameter
Address Setup before ALE Low
Controller ALE Pulse Width
Address Hold after ALE Low
RD*/WR* High to ALE High
Address/Select to WR* High
Address/Select to RD* Low
RD* Pulse Width
(1)
WR* Pulse Width
RD* Low to Data Available
Read Data Hold Time
(2)
Min.
7
34
10
10
117
17
3 × tcyc
100
—
3
Typical
—
—
—
—
—
—
—
—
—
—
Max.
—
—
—
—
—
—
—
—
30
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100441E
Conexant
4-1
CONEXANT [ CONEXANT SYSTEMS, INC ]
