CN8330
DS3/E3 Framer with 52 Mbps HDLC Controller
4.0 Mechanical/Electrical Specifications
4.1 Timing Requirements
and
through
illustrate the clock and data
relationships for all output and input signals. Propagation delays for the output
signals are listed below. The output signal timings are relative to the listed edge of
the clock. Clock outputs derived from clock inputs are listed with the edge as
both. This means that the delay number given applies for either edge. Input
signals should have setup and hold times with respect to the listed edge of the
given input clock. All times are listed in nanoseconds and are measured with
30 pF loading on the output pins.
Table 4-2. Clock Timing Requirements
Timing Requirements
Low Pulse Width -
ρ
wl
High Pulse Width -
ρ
wh
Cycle Time - t
cyc
Cycle Time
Low Pulse Width
High Pulse Width
Clock
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
RXCKI, DS3CKI, TXCKI
—
RXBCK
RXBCK
Min.
5.0
5.0
19.0
—
6 RXCKI
2 RXCKI
Typical
(44.736 MHz)
11.2
11.2
22.4
Typical
(34.368 MHz)
14.55
14.55
29.1
Units
ns
ns
ns
ns
8 RXCKI
—
—
—
—
ns
ns
Figure 4-2. Output and Input Signal Timing
pwl
Input
Clock
Input
Signal
pwh
Clock
Output
Signal
tsu
tpd
thd
100441E
Conexant
4-3
CONEXANT [ CONEXANT SYSTEMS, INC ]
